Flash memory are used to store information in digital cameras and other handheld devices

18.4 Chapter Summary

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Flash memory can be used to store data that you want to retain across power cycling of the PIC32.

Program flash memory is divided into 128 pages of 4 kB each. Each page is divided into eight rows, each consisting of 128 four-byte words.

Flash can only be erased a page at a time, by setting all bits to ones. Writes can only flip ones to zeros, never zeros to ones. Writes can only be done to a single four-byte word or an entire row at once.

Flash has a limited lifespan so you should minimize writes and erasures.

2.2.2 Example of USB Flash Memory

USB flash memory is simply a data storage device that contains non-volatile flash memory and an integrated USB interface. Relative to middleware, some of the key features of interest regarding USB Flash memory include:

Capacity. The size of the USB flash memory.

Operating System (Device Driver) Support. What operating system distributions include device drivers for the USB Flash memory. If the embedded system's operating system is not on that list, then a device driver will need to be created/ported and integrated.

Formatted. Does the USB Flash memory come pre-formatted, in support of a particular file system, for example. The USB Flash memory may need to be erased and reprogrammed, as necessary, in support of a particular middleware.

Sector Size. The smallest block of Flash that can be erased and/or programmed. The reader should also note whether there are any restrictions when reading the Flash.

Author Note

USB Flash memory can also be referred to by other names in the field, such as USB Flash Memory Keys, USB Flash Memory Drives, USB Flash Memory Sticks, and USB Flash Memory Pen Drives to name a few. If it is Flash memory that is hot-swappable into a USB port, then it falls under this category of USB Flash memory hardware.

As shown in Figure 2.7a, USB Flash memory is a small PCB (printed circuit board) that is enclosed in a durable chassis, and is powered via the connection to the embedded system's USB port. A standard USB interface that adheres to the industry standard USB specification, such as USB 1.1 or USB 2.0, extends from this small chassis that allows the stick to be plugged into a board's USB drive port as shown in Figure 2.7b. This device is typically smaller than other portable storage mediums, and is hot-swappable into a board's USB port that has device driver support for the particular type of USB Flash memory.

The real-world USB Flash memory datasheets shown in Figures 2.8a and 2.8b show some additional flash specification information that is useful for programmers to know regarding support of Flash types of storage mediums (see highlighted portions of datasheets).

III.B.5 Flash Memory

Flash memory is specially-arranged EEPROMs, occupying a smaller area than EEPROM or DRAM arranged in other structures. Consequently, on a given chip area, flash memory with greater memory capacity than DRAM can be manufactured inexpensively. Also, hundreds to tens of kilobytes of data can be simultaneously erased, unlike other types of EEPROM. But unlike other types of EEPROM whose addresses can be selectively rewritten, all memory addresses in one block in flash memory are erased and then each memory address in the block can be written individually. This is inconvenient because even if we want to rewrite only one address, we have to rewrite the entire block.

A flash memory is currently structured in at least four different ways with different features. They are NOR type, NAND type, AND type, and DINOR type. The first two types have been widely used. A NOR-type flash memory is illustrated in Fig. 15. If one memory word consists of 8 bits, we have bit lines, D1, D2, … , D8. All these lines are connected to the drains of MOSFETs with floating gates. A1, A2, … , AK are the outputs of a memory address decoder, which are connected to the gates of MOSFETs with floating gates and only one of which has a high voltage when the decoder is active. All sources of MOSFETs with floating gates are connected to S, which means a source. Applying appropriate voltages to S, Di and Aj, writing, reading, or erasure is done. White circles denote contact windows between aluminum lines and drains. A NAND-type flash memory is illustrated in Fig. 16. Reading time in NOR-type flash memory is about hundreds of nanoseconds or less, being comparable to ROMs, but is faster than the NAND-type, though its area is larger (because of more contact windows which occupy large areas). Erasure and writing time in both types is a few microseconds, being far slower than RAMs, but is far faster than hard disks whose writing time is tens of milliseconds.

Flash memory has one serious shortcoming. If writing is repeated many times, flash memory gradually requires longer writing time and eventually stops working because of fatigue. Currently, we can repeat writing close to a million times and this is three orders of magnitude smaller than hard disks.

Flash memory is cheaper with greater memory capacity than DRAM and yet faster, though more expensive per bit, than hard disks. Flash memory is immune to vibration, dust, and mechanical shocks. Also, flash memory works with far less power consumption, and accordingly if flash memory is installed in a notebook computer, replacing a hard disk, then batteries last far longer. A hard disk consumes a few amperes at the start and then consumes tens of milliamperes for rotation after that. In contrast, a flash memory in power-down mode consumes only a few microamperes. Flash memory has many unique applications. Flash memory is used in upgradable BIOS (Basic Input Output System), which is the hardware part of an operating system of some personal computers, and also in modems. Flash memory is widely used as credit-card-sized memory cards, which are called PCMCIA (personal computer memory card international association), for portable computers, as handy memory extensions. In digital cameras, photographic images are stored in flash memory. Flash memory is also used in cellular phones, where the identification of the owners and programs are stored and updated by wireless transmission. Flash memory is also used in pocketable recorders that record voice without microcassettes, i.e., without mechanical drives. Such pocketable recorders are far smaller than conventional pocketable recorders, and batteries last far longer. Flash memory is used also in FPGAs, as explained later.

Abstract

Flash memory-based solid state drives (SSDs) have become ubiquitous in modern computing systems, such as high-performance servers, workstation, desktops, and laptops, due to their performance and density. The architecture of SSDs has evolved to exploit the advantages of flash memories and at the same time conceal their shortcomings. SSD concurrency techniques such as channel striping, flash-chip pipelining, die interleaving, and plane sharing utilize the available parallelism of flash memories, while the flash translation layer (FTL) operations minimize the latency overhead of flash memories. This chapter provides a comprehensive survey of SSD topics that span across from the physical properties of a flash memory cell to the architecture of SSDs. The FTL-related topics are discussed in the context of inter-related system-level operations, which include address mapping, garbage collection, wear leveling, bad block management, SSD concurrency techniques, and page allocation strategies. This chapter also surveys recent research efforts on SSDs.

Flash

Flash memory is a low-cost, high-density, non-volatile computer storage chip that can be electrically erased and reprogrammed. Flash memory can be either NOR-Flash or NAND-Flash. NOR-Flash allows a single word to be written or read independently. It can be used for storing boot code. NAND-Flash is denser and cheaper than NOR-Flash. It is block-accessible and cannot be used for storing code. It is primarily used in memory cards, USB flash drives, and solid-state drives.

FLASH MEMORY CARDS

Flash memory cards and sticks are a popular medium for storing and transferring varying amounts of data.

Memory cards typically range in size from 8 to 512 MB, but new cards are capable of storing upwards of 8 GB of data.

Commonly used for storing photos in digital cameras and for storing and transferring programs and data between handheld computers (pocket PCs and Palm OS devices).

Flash memory cards include:

Secure Digital (SD) Memory Card

CompactFlash (CF) Memory Card

Memory Stick (MS) Memory Card

Multi Media Memory Card (MMC)

xD-Picture Card (xD)

SmartMedia (SM) Memory Card

LT1109 generates VPP for flash memory

by Steve Pietkiewicz

Flash memory chips such as the Intel 28F020 2Megabit device require a VPP program supply of 12 volts at 30mA. A DC-DC converter may be used to generate 12 volts from the 5 volt logic supply. The converter must be physically small, available in surface-mount packaging, and have logic-controlled shutdown. Additionally, the converter must have carefully controlled rise time and zero overshoot. VPP excursions beyond 14 volts for 20ns or longer will destroy the ETOX-process based device.

Figure 33.18’s circuit is well suited for providing VPP power for single or multiple flash memory chips. All associated components, including the inductor, are surface mount devices. The SHUTDOWN¯ input turns off the converter, reducing quiescent current to 300μA when pulled to a logic 0. VPP rises in a controlled fashion, reaching 12 volts ±5% in under 4ms. Output voltage goes to VCC minus a diode drop when the converter is in shutdown mode. This is an acceptable condition for Intel flash memories and does not harm the memory.

Flash memory

Flash memory is a long-life and non-volatile storage chip that is widely used in embedded systems. It can keep stored data and information even when the power is off. It can be electrically erased and reprogrammed. Flash memory was developed from EEPROM (electronically erasable programmable read-only memory). It must be erased before it can be rewritten with new data. The erase is based on a unit of a block, which varies from 256 KB to 20 MB.

There are two types of flash memory which dominate the technology and market: NOR flash and NAND flash. NOR flash allows quick random access to any location in the memory array, 100% known good bits for the life of the part and code execution directly from NOR flash. It is typically used for boot code storage and execution as a replacement for the older EPROM and as an alternative to certain kinds of ROM applications in embedded systems. NAND flash requires a relatively long initial read access to the memory array compared to that of NOR flash. It has 98% good bits when shipped with additional bit failure over the life of the part (ECC is highly recommended). NAND costs less per bit than NOR. It is usually used for data storage such as memory cards, USB flash drives, solid-state drives, and similar products, for general storage and transfer of data. Example applications of both types of flash memory include personal computers and all kinds of embedded systems such as digital audio players, digital cameras, mobile phones, video games, scientific instrumentation, industrial robotics, medical electronics and so on.

The connections of the individual memory cells in NOR and NAND flash are different. What’s more, the interface provided for reading and writing the memory is different. NOR allows random access for reading while NAND allows only page access. As an analogy, NOR flash is like RAM, which has an independent address bus and data bus, while NAND flash is more like a hard disk where the address bus and data bus share the I/O bus.

8.3 Flash Memory Devices

Flash memory devices store large quantities of data in a small area using stacked memory cells. The density of such cells is increasing substantially to cater for the demand of storing more data in a smaller area. In the quest to achieve this goal, the flash memory technology is being constrained with multilevel cells (MLC), where a single memory cell is designed to store more bits of data by using multiple logic levels [24]. Traditionally, a single memory cell could hold only one non-zero charge level for storing 1-bit of data. As the memory technology is moving towards MLC and more complex forms in 3D structures [25], there is an even greater challenge to counter errors introduced while storing and retrieving data from such devices. The increase in the number of levels (means reduced distance between the levels) in the cells may result in variations in cell behavior because of cell-to-cell interference. It also reduces signal-to-noise ratio while reading data from the memory stack [26]. Other factors such as random telegraph noise (RTN), retention noise due to electrons leaking from floating gate, and wear/tear of the cells substantially affect the reliability of stored data in the memory. Therefore, using an efficient error correction technique is highly crucial for safeguarding and recovering critical data from the storage devices. LDPC codes have been largely promising in dealing the data integrity issues faced by memory devices using ultra innovative storage solutions [26]. LDPC codes are already being used as a reliable error correction technique in a number of storage devices in the industry. For example, LDPC codes are used as media error correction in SSD [27] cards SanDisk X400 and Seagate Nytro.

A flash storage device typically consists of a memory controller and flash memory stack in a single package. The controller is the common interface between the host and the flash memory. It moderates and supports various protocols (USB, PCI, UFS, etc.,) involved in the host communication with the device. A block diagram of a simple memory device package is shown the Fig. 8.1.

For writing data to the flash storage in a memory device, the host data is first buffered through a host interface. The CPU controls the LDPC encoding operation on the host data read from memory buffers. The encoded data is then buffered before storing it in the flash memory via flash interface. A similar process is followed for reading data from flash storage. The data read from the flash memory is decoded using a LDPC decoder. Errors that are introduced by faulty flash storage cells are corrected by the LDPC decoder using multilevel error correction schema [28]. The corrected data is then sent to the host via the memory buffers and host interface. For soft-decision decoding, the soft information is obtained by performing multiple reads with varied word-line voltages. The hard-decision decoding scheme is first used for error correction. In case of correction failure, soft-decision decoding [28] with higher levels of sampling and quantization scheme is attempted in stages for correcting the errors.

8.16 Implementing indices in flash memories

The following discussion is based on (Fevgas et al., 2020) which discuss placing indices in flash SSDs, rather than magnetic disks. Treating SSDs as simply another category of block devices ignores their idiosyncrasies, like erase-before-write, wear-out and asymmetric read/write, and may lead to poor performance. These peculiarities of SSDs require reinvention of the indexing techniques that have been designed primarily for HDDs. In this work, we present a concise overview of the SSD technology and the challenges it poses. The article surveys 62 flash-aware indexes for various data types, analyze the main techniques they employ, and comment on their main advantages and disadvantages, aiming to provide a systematic and valuable resource for researchers working on algorithm design and index development for SSDs. Additionally, we discuss future trends and new lines of research related to this field.

Flash memories were introduced in Chapter 2. Byte addressable NAND cells could use only a single voltage threshold storing it. Single Level Cell - SLC, MultiLevel Cell - MLC, Triple Level Cells - TLC, Quadruple Level Cell - QLC storing single, two, three, four bits per cell, exploiting multiple voltage thresholds. QLC flash provides higher capacities for read-intensive applications, but is slower and less durable than MLC and TLC. Another method to increase flash storage density is to stack flash cells in layers, as in 3D NAND or Vertical NAND - V-NAND and up to 64-layer chips are available, while 96-layer TLC NAND has been introduced Three important features of NAND memories are as follows (Micheloni et al., 2010).

Asymmetric read/write latencies: reads are faster than writes.

Writes are slow because an erase-before-write, which means that in place updates unlike HDDs triggers a number of reads and writes in flash devices.

Flash memories have a limited life cycle: every flash cell exhibits a high bit error rate (wear-out) after a certain number of program/erase cycles have been performed. Uneven writing of the pages may render whole areas completely unreliable or unavailable.

To hide or even alleviate some of these peculiarities, SSDs provide the Flash Translation Layer - FTL, which runs on the device controller and employs an out-of-place policy, using logical address mapping, and takes care of wear leveling, space reclamation, and bad block management. Thus, SSDs operate as block devices through FTL.

Traditional indices will perform poorly if they are directly written to SSDs, e.g., B+trees during updates generate small random writes, which may lead to long write times.

SSD's Host Interface Controller is connected to a CPU with an SRAM cache, which holds the firmware and DRAM controller and multiple flash controllers connected via dedicated channels to flash packages.

NVM express - NVMe is an optimized, high-performance scalable host controller interface designed to utilize PCI express - PCIe based solid-state storage. NVMe provides efficient access to storage devices built with NVM. The performance metrics addressed by NVMe are bandwidth, I/Os per second - IOPs, and latency. The maximum IOPs possible for Serial ATA was 200 KIOPS whereas NVMe devices can exceed 1,000 KIOPs. By supporting PCIe and Fabrics such as Remote Direct Memory Access - RDMA and Fibre Channel.

https://en.wikipedia.org/wiki/Remote_direct_memory_access

NVMe can support much higher bandwidths than SATA or Serial Attached SCSI - SAS

https://en.wikipedia.org/wiki/Serial_ATA

https://en.wikipedia.org/wiki/Serial_Attached_SCSI

Finally, next generation memory technologies may have read access latency under a microsecond, requiring a streamlined protocol that enables an end-to-end latency of under 10 microseconds, including the software stack.

NVMe is a completely new architecture for storage, from the software stack to the hardware devices and systems. Unlike SAS and SATA protocols NVMe protocol supports multiple deep queues. Typical SAS devices support up to 256 commands and SATA devices support up to 32 commands in a single queue. These were adequate for hard disk drive technologies, but cannot take full advantage of current and next-generation NVM technologies. In contrast, NVMe supports 64K commands per queue and up to 64K queues. These queues are designed such that I/O commands and responses to those commands operate on the same processor core and can take advantage of the parallel processing capabilities of multi-core processors. Each application or thread can have its own independent queue, so no I/O locking is required.

FTL obscures flash idiosyncrasies by providing a standard interface with the host system. The main functions of FTL are address mapping, wear leveling, garbage collection, and bad block management. FTL implements an out-of-place update policy, since flash cells cannot be updated in-place. It marks old pages as invalid and writes the updated data into clean locations. It hides the complexity of programming the flash cells, maintaining a logical to physical address mapping mechanism. Three different mapping methods have been proposed, which differ from the viewpoint of mapping granularity: page-level, block-level, and hybrid (Kwon et al., 2011).

Out-of-place updates leave flash pages invalidated; thus, FTL initiates a garbage collection procedure to reclaim free space for incoming data (Cornwell, 2012). Garbage collection is invoked when the drive is idle or runs out of free pages. It exploits the pages utilization index and invalid total pages to select the proper blocks (Kwon et al., 2011) Next, it copies any valid pages of the candidate blocks into new positions, and performs the erases. Continuous erase operations wear flash memory cells and FTL provides a wear leveling mechanism to protect them from premature aging. It distributes the erasures uniformly across all medium, utilizing an erasure counter for each erase block. SSDs contain bad blocks, which occurred during operation, or even preexisted as a result of the manufacturing process. FTL handles defective blocks through address mapping. When a block is recognized as faulty, its data is copied to another functional block and it is marked as bad for future use.

Large batches of parallel I/Os are to be utilized to ensure that SSDs internal parallelization and NVMe protocol are fully exploited. In-memory buffering is a prerequisite for batched I/O and it also accelerates the performance of indices, since it reduces the number of accesses to secondary storage. Proposed methods exploit in memory buffers for logging, overflow nodes and use batch write or/and read operations.

Early works used batch writes to alleviate the difference between reads and writes, whereas more recent ones target internal parallelization. Batched I/O exploits the internal parallelization and the potentials of the NVMe protocol in a more efficient way, thus better performance is achieved. They also eliminate small random write operations that may cause frequent garbage collection operations and fragmentation of the FTL mapping table; this is highly dependent on the proprietary mapping algorithm of FTL.

The large batches of random reads also exploit the internal parallelization of SSDs and the efficiency of the NVMe protocol. Additionally, they do not differ much, in terms of performance, from the sequential ones. Using large I/O batches, besides accelerating the performance of reads and writes, results also in the separation of reads and writes, limiting the interference between them.

Open-Channel architecture proposal does not have a firmware FTL implemented on the device, but instead leaves the management of the physical solid-state storage to the computer's OS.

https://en.wikipedia.org/wiki/Open-channel_SSD

Elevating commodity storage with the SALSA host translation layer is relevant to this discussion (Ioannou et al., 2018).

Flash-based indices can be categorized as follows:

(1 and 2) FTL and raw based B-trees.

(3) Skip lists.

(4 and 5) FTL and raw based hash indices.

(6 and 7) FTL and raw based PAM indices.

(8) FTL based SAM indices.

(9) Generic frameworks.

(10 and 11) FTL and raw based inverted indices.

Examples of indexes in various categories are provided in the paper.

In a recent study Bianca Schroeder et al. studied the reliability of modern file systems in the face of SSD errors (Jaffer et al., 2020). File systems considered are ext4, Btrfs, and F2FS. Different SSD error modes are considered and fault injection is used to explore error cases. The results indicate that in 16% of cases a file system cannot be mounted or repaired. Key file metadata structures that can cause such failures and design guidelines for file systems deployed in SSDs are given in Table 8.7.

Table 8.7. Table (10) in (Fevgas et al., 2020) lists different types of flash errors and their manifestation in the file system: (a/b) Read/Write I/O Error, (c) Corruption, (d) Shorn write, (e) Lost write.